/*
    模块注解：
    clk0为1Hz脉冲输入，进行计时
    clr为异步清零信号，将系统设为出厂状态,低电平有效
    settime为同步信号，将set中的预置时间发送到cnt中

*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock is
  port(clk0:in std_logic;
       clr:in std_logic;
       settime:in std_logic;
       choice:in std_logic_vector(2 downto 0);
       add10_hour:in std_logic;
       add1_hour:in std_logic;
       add10_min:in std_logic;
       add1_min:in std_logic;
       add10_sec:in std_logic;
       add1_sec:in std_logic;
       fqout:out std_logic_vector(26 downto 0);   
       ring:out std_logic);
end;

architecture art of clock is
component divider
    port (clk:in std_logic;
        	clk1Hz: out std_logic );
end component;

component cnt60_sec is
	port(clk_sec:in std_logic;--clock signal (1Hz)
		set_sec:in std_logic;--set time enable
		clr:in std_logic;--clear
		qin_sec:in std_logic_vector(7 downto 0);--8421 code from set entity
		qout_sec:out std_logic_vector(7 downto 0);--output 8421 code
		carry_sec:out std_logic;--carry bit for min
		);
end component;

component cnt60_min is
	port(clk_min:in std_logic;--clock signal(carry signal from cnt60_sec.vhd)
		set_min:in std_logic;--set time enable
		clr:in std_logic;--clear
		qin_min:in std_logic_vector(7 downto 0);--8421 code from set entity
		qout_min:out std_logic_vector(7 downto 0);--output 8421 code
		carry_min:out std_logic;--carry bit for hour
		);
end component;

component cnt24_hour is
	port(clk_hour:in std_logic;--clock signal(carry signal from cnt60_min.vhd)
		set_hour:in std_logic;--set time enable
		clr:in std_logic;--clear
		qin_hour:in std_logic_vector(7 downto 0);--8421 code from set entity
		qout_hour:out std_logic_vector(7 downto 0)-- output 8421 code
		);
end component;

component set_sec is
    port(add10: in std_logic;
        add1: in std_logic;
        qout_sec:out std_logic_vector(1 downto 0));
end component;

component set_min is
    port(add10: in std_logic;
        add1: in std_logic;
        qout_min:out std_logic_vector(1 downto 0));
end component;

component set_hour is
    port(add10: in std_logic;
        add1: in std_logic;
        qout_hour:out std_logic_vector(1 downto 0));
end component;

component screen 
   port(qin_hour:in std_logic_vector(2 downto 0);
		qin_min:in std_logic_vector(2 downto 0);
		qin_sec:in std_logic_vector(2 downto 0);
        fqout:out std_logic_vector(26 downto 0);
        ring:out std_logic);
end component;

signal clk_minute:std_logic;
signal clk_second:std_logic;
signal sout_hour:std_logic_vector(7 downto 0);
signal sout_min:std_logic_vector(7 downto 0);
signal sout_sec:std_logic_vector(7 downto 0);
signal time_hour:std_logic_vector(7 downto 0);
signal time_min:std_logic_vector(7 downto 0);
signal time_sec:std_logic_vector(7 downto 0);

begin

u1:cnt24_hour port map(clk_hour=>clk_minute,set_hour=>settime,clr=>clr,qin_hour=>sout_hour,qout_hour=>time_hour);
u2:cnt60_min port map(clk_min=>clk_second,set_min=>settime,clr=>clr,qin_min=>sout_min,qout_min=>time_min);
u3:cnt60_sec port map(clk_sec=>clk0,set_sec=>settime,clr=>clr,qin_sec=>sout_sec,qout_sec=>time_sec);

u4:set_hour port map(add10=>add10_hour,add1=>add1_hour,qout_hour=>sout_hour);
u5:set_min port map(add10=>add10_min,add1=>add1_min,qout_min=>sout_min);
u6:set_sec port map(add10=>add10_sec,add1=>add1_sec,qout_sec=>sout_sec);

u7:screen port map(qin_hour=>time_hour,qin_min=>time_min,qin_sec=>time_sec,fqout=>fqout,ring=>ring);

end art;

